Exemplary embodiments relate to a method of programming a nonvolatile memory device.
There is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and can retain data even without the supply of power. To develop high-capacity memory devices capable of storing a large amount of data, technology for the high integration of memory cells is being developed.
Recently, to further increase the degree of integration of memory devices, active research has been performed on a multi-bit cell which is able to store plural data in a single memory cell. This type of a memory cell is called a multi-level cell (MLC). A memory cell capable of storing one bit is called a single level cell (SLC).
FIG. 1 is a flowchart illustrating a known operation of programming a nonvolatile memory device.
The program operation of FIG. 1 illustrates only a process of performing a most significant bit (MSB) program operation after a least significant bit (LSB) program operation in the nonvolatile memory device, including memory cells each capable of storing data of 2 bits.
Referring to FIG. 1, first, a program command, addresses, and data to be programmed are inputted to a nonvolatile memory device at steps S101, S103, and S105, respectively. An execution command is then inputted to the nonvolatile memory device at step S107.
In response to the execution command, a program operation is performed at step S109, and verification operations using first to third verification voltages PV1 to PV3 are then performed at steps Sill to S115, respectively.
When the program operation is performed, a program voltage Vpgm is supplied to a word line for a program, and the first to third verification operations using the first to third verification voltages PV1 to PV3 are performed.
The program process is finished when all the first to third verification operations are a pass. If the first to third verification operations are not a pass, the program voltage Vpgm is raised, and the program operation is performed again using the raised program voltage Vpgm. Here, the program voltage Vpgm is increased from a program start voltage Vpgm_start by a step voltage according to an increment step program pulse (ISPP) method.
FIG. 2 shows the levels of voltages supplied to a selected word line in response to program pulses.
Referring to FIG. 2, a program voltage, raised from a program start voltage Vpgm_start by a step voltage, is supplied in response to a program pulse. After the program voltages are supplied, first to third verification voltages PV1 to PV3 are supplied. Here, the first to third verification voltages PV1 to PV3 are not separately shown, but shown as one program verification pulse.
As shown in FIG. 2, the program start voltage Vpgm_start at which the program operation is actually started is 15 V. During the time when some program pulses are supplied, only the first verification operation PV1 is performed. Next, the second verification operation PV2 and the third verification operation PV3 are performed. This is because, during the time when the program operation is first started in response to some program pulses, the threshold voltages of all memory cells do not rise to the extent that they become a pass for the second and third verification voltages PV2 and PV3.
From FIG. 2, it can be seen that a program voltage of 13 V, which is less than the program voltage supplied when the program operation is actually started, is first supplied. The reason why a program voltage less than a program voltage supplied when a program operation is actually started is first supplied is because the threshold voltage of a memory cell shifts in response to the erase/write cycles of the memory cell.
With an increase in the number of erase/write cycles, electrons are trapped at the memory cell, and so a threshold voltage of the memory cell becomes higher than its initial threshold voltage even after the memory cell is erased. Although a program voltage of 15 V can be first supplied, if the program voltage of 15 V is subsequently supplied, memory cells become over programmed. Therefore, to prevent this problem, a program voltage of 13 V is initially supplied. It can be said that memory cells start to be programmed when the program voltage of 15 V is supplied for the first time. A method of supplying a program voltage as described above is referred to as a blind program method. In other words, during the time when the blind program voltage of 13 V to 15 V is supplied, there is no program effect resulting from the supply of the program voltage. If the number of erase/write cycles is high, a program operation can be normally performed in response to a program voltage starting at 13 V.